1. Field of the Invention
The invention relates generally to a clock scheme in a microprocessor and, more particularly, to dynamic power management in an execution unit of a microprocessor using pipeline wave flow control.
2. Description of the Related Art
Today's microprocessors designed in CMOS technology dissipate more and more power. Thus, cooling microprocessors, as well as supplying sufficient power, becomes a challenge. In CMOS technology, power dissipation is due to charging and discharging capacitances introduced by a following stage of circuits and the connecting wires. Typically, power dissipation ‘P’ is proportional to the frequency ‘f’ of switching the capacitive load of all circuits and is also proportional to the square of the supply voltage ‘Vt’. Thus, Pαf*Vt**2.
In addition, as processor speeds increase, execution units within a processor must implement deeper pipelines in order to meet the smaller cycle times. This represents an increase in the amount of power needed due to register clocking and switching. However, execution units typically do not operate at 100% utilization, but operate at 10-20% utilization. Thus, much of this power usage is unnecessary. That is to say, for at least 80% of the time when there are no instructions flowing in the pipelines, power is still being consumed due to register clocking and switching.
Therefore, there is a need for controlling a pipeline of an execution unit in a microprocessor such that when no valid instructions are being executed, the clock to each unused stage in the pipeline is dynamically controlled so that no switching occurs and power is conserved.